Microelectromechanical systems (MEMS) have progressed from research prototypes to a pervasive technology platform underpinning both high-end industrial applications and widely adopted consumer products. Their presence across domains such as automotive, medical diagnostics, mobile electronics, and precision instrumentation illustrates the degree to which MEMS have become fully established in modern electronic-based systems. In this context, device statistics serve as a rigorous framework for benchmarking performance within specific device concepts, enabling systematic evaluation of design, reliability, and functional efficiency. Independent of the application field, standard device architectures in MEMS require the integration of one or more thin films to achieve the targeted functionality. The thin films are either grown on the substrate or bonded to the substrate, resulting in a stacked material system at wafer level with two or more layers of different materials, including interfaces. Due to these challenging batch-compatible thin film fabrication processes and subsequent micromachining for the MEMS device fabrication, any tolerances from each fabrication step add up, which may result in output performance parameters out of the acceptable limits. Over the past 30 years, the MEMS industry has relied on statistical metrology to gain insights into individual device variations, both at wafer level and throughout entire fabrication batches, as described by . However, only a limited number of publications have so far discussed statistical approaches. Recently, this topic was addressed for resonantly operated MEMS , where, in the latter study, hundreds of pure single-crystalline silicon cantilevered resonators were evaluated with respect to mode-dependent resonance frequencies and quality factors.

For resonating devices, local change of the film stress and also the thin film thickness affect the properties of the MEMS devices and make precise local monitoring of these parameters necessary even during the fabrication of MEMS devices. However, the local film stress is influenced by several contributions in material stacks , like different lattice parameters and coefficients of thermal expansion (CTE) . The crystallinity of the layer – whether amorphous, polycrystalline, or single-crystalline – further influences stress. In single crystals, it may stem from doping or point defects, whereas in polycrystalline films it is linked to growth processes and grain boundary formation . Techniques like physical vapor deposition (PVD) or magnetron sputtering can strongly modify stress due to the bombardment with energetic particles, not only affecting the surface of the thin film but also penetrating into the surface-near bulk region of the material, so that the crystal lattice gets surface-near distorted or gas atoms from the plasma atmosphere get trapped in the film .

Many techniques have been developed to measure the film stress at wafer level or locally at a specific position. Different approaches are classified by into (1) techniques measuring wafer curvature, (2) material-level nondestructive measurements, (3) specimens and structure characterization techniques, and (4) material-level destructive measurements.

While the measurement of the curvature can be performed either at wafer level (mainly with capacitive techniques) or on smaller snippets (mainly with optical techniques), Stoney's equation is used in most cases to calculate the stress . Therefore, the thicknesses of the device layer and substrate need to be known, but a local variation in the parameters cannot be taken into account, and only an averaged stress value across the sample is calculated. However, since curvature measurements are fast and easy to implement in the fabrication process of MEMS devices, they are widespread in industry and academia .

Available stress measurement techniques, however, are typically limited to specific components of the stress tensor. In particular, XRD and FIB milling are advanced techniques compared to others and are time- and cost-intensive. Moreover, absolute stress values obtained from different methods are often difficult to compare, since the measurement principles impose limitations such as averaging over volumes and crystallographic directions. This also prevents the application of otherwise useful models, for example, the approximation of uniaxial residual stress as the superposition of a constant mean stress and a gradient stress demonstrated by . WLI, by contrast, offers a fast and versatile approach that can be readily applied to a broad range of quality inspection tasks, such as surface characterization or the analysis of effects in micromachined beams . In this work, WLI is employed as an optical profiling technique to determine both the local device layer thickness, via scans of trenches in the device layer in the area of the silicon frame, and the static deflection of cantilevers with different orientations on the wafer, thereby enabling the extraction of orientation-dependent residual stress values.

The present study describes a passive MEMS structure to simultaneously measure the local device layer thickness and the orientation-dependent static deflection of a cantilever. An automated contactless WLI setup is constructed and used to scan hundreds of devices fabricated on different single- and polycrystalline device layers of 4-inch (100 mm) wafers. Considerations on stress in a bent beam enable the calculation of local stress values from the measurement of the actual device layer thickness and static deflection of the cantilever and when knowing the Young's modulus and Poisson's ratio, respectively. By doing so, we are able to obtain for each device individually the information on thickness and the uniaxial deflection, hence the local uniaxial residual stress as a superposition of a mean stress and a gradient stress.

The residual stress in a thin film can be expressed in general form via the stress tensor σ: 1σ=σ11σ12σ13σ21σ22σ23σ31σ32σ33. Within the study of slender beams, we focus on the uniaxial residual stress along the beam axis, leading to the beam's deformation. Hence, the total uniaxial residual stress deforming the slender beam is represented by the polynomial 2σuniaxial=∑k=0∞σkzh/2k, where h is the thickness of the beam and z is the coordinate across the thickness with the zero point in the midplane of the beam. Following the argumentation of , we consider the constant mean stress σ0 and the gradient stress σ1 only. They can be attributed to a mismatch of the thermal expansion coefficient between the thin film and substrate and to local effects, including graining (e.g., size and distribution) and structural defects in the thin film, respectively. This leads to the simplified form of the uniaxial stress: 3σuniaxial=σ0+σ1zh/2. The first term subsumes symmetric stress components, and the latter one represents anti-symmetric components. Furthermore, following the work of , the distinction between tilt and curl deformations is introduced, related to the mean and the gradient stress, respectively. They approximate the deflection shape of the beam with a quadratic function: 4z(x)≈θ0+θ1x+12Rx2, where x is the coordinate along the beam axis, R is the constant radius of the curvature, and θ0 and θ1 are the total angular rotation of the thin film at the anchor. calculate θ0 and θ1 via a finite element method (FEM) as 5θ0≈σ0E(1.33+0.45ν)(-0.014h+1.022)θ1≈σ1E0.0086h2-0.047h+0.81, where E and ν are the Young's modulus and the Poisson's ratio of the thin film, respectively. Additionally, σ1 is indirectly proportional to R, as σ1=Eh/2R.

The separation into tilt and curl is illustrated in Fig. . In Fig. a and b, the mean stress σ0 is negative, equal to a downwards tilt. The superposition of a negative gradient stress further curls the beam down, as shown in Fig. a. In Fig. b, the superposition with positive σ1 results in a positive value of the 500 µm long cantilever for the deflection at the tip z(x=500 µm), already for σ1=10 MPa, which is 2 orders of magnitude lower than the absolute value of σ0. In Fig. c and d, σ0 is positive; hence the tilt points upwards. Again, the superposition with σ1 leads to an additional curl in the corresponding direction. In Fig. c, similarly to Fig. b, a gradient stress 2 orders of magnitude smaller than the mean stress is able to change the sign of the static deflection at the tip of the cantilever. In conclusion, it can be stated that the amplitude of the static deflection depends much more on σ1 than on σ0. This behavior of the static deflection can also be seen in Eq. (), where σ1 contributes to both the linear and the quadratic term, while σ0 only affects the linear term.

Different silicon, 3C-SiC, and diamond device layers with various thicknesses, microstructures, and mechanical properties are investigated on phosphorus-doped 〈100〉-oriented silicon substrates covered with a wet thermal oxide, summarized in Table . The deposition of polycrystalline 3C-SiC is performed in an LPCVD system. An alternating supply deposition (ASD) working with alternating gas flows of propane and silane with intermediate pump-out times is utilized, as described in . Polycrystalline diamond (PCD) thin films from CarbonCompetence GmbH are fabricated in an HFCVD system at elevated temperatures from methane and hydrogen as precursor gases. For deposition of the PCD films with grains of several micrometers in diameter (m-PCD) and PCD films with small grains in the range of several nanometers (n-PCD), the temperature of the Si substrate was set to 800–850 °C and a total gas pressure of 5 mbar was applied, while the filament-to-substrate distance was maintained at 50 mm. The applied gas flows for the deposition of m-PCD and n-PCD films are set to CH₄ / H₂ ratios of 0.1% and 2%, respectively. Further details on the deposition parameters can be found in and . The grown thin films are benchmarked with single-crystalline silicon (SCSi) from a commercially available SOI wafer and with polycrystalline silicon (PCSi), as these are standard materials for MEMS devices. Two depositions of PCSi in an LPVCD system are performed at different temperatures, leading to very small nanosized silicon grains (s-PCSi) at a deposition temperature of 568 °C and larger grains by 2 orders of magnitude (l-PCSi) at a deposition temperature of 600 °C.

A Bosch process is used for micromachining single- and polycrystalline silicon. Furthermore, we developed suitable dry-etching recipes for PCSiC and PCD in a capacitively coupled plasma (CCP), STS RIE, and in an inductively coupled plasma reactive ion etcher (ICP RIE), Oxford Plasmalab 100, summarized in Table . We achieved an etching rate up to 100 nm min⁻¹ for PCD and up to 150 nm min⁻¹ for PCSiC, while for the selected etching parameters, the etch rate depends on the grain size of the polycrystalline device layer.

Test structures consisting of a cantilever and a step profile (SP) close to the anchor region are presented in Fig. a. The SP consists of 50 µm wide trenches etched through the device layer, down to the buried oxide. By utilizing the Bosch process, the cantilevers are released from the substrate, whereas the stress in the device layer leads to a static deflection. Cantilevers with a constant length of 500 µm and a width of 50 µm were fabricated to characterize the local stress distribution.

A Micro System Analyzer (MSA-400) from Polytec GmbH, equipped with a 10 times magnifying Mirau objective and a piezoelectrically actuated stage, is used for static device characterization. An automated measurement setup is constructed to scan many devices fabricated on the same wafer at different positions for analyzing device layer thickness and film stress with WLI. To position the wafer below the objective, three motorized linear stages from Zaber Technologies Inc. are used both for the in-plane positioning and to focus on each device. A horizontal x-stage (X-LSM100A), a horizontal y-stage (X-LSM150A), and a vertical z-stage (X-VSR20A) with travel ranges of 100, 150, and 20 mm, respectively, are mounted on a vibration-damped table. Further on, each position stage, along with the MSA-400, is controlled with the same script to ensure an automated scan of all the devices at wafer level. A schematic representation of the measurement setup is shown in Fig. b.

From the three-dimensional scan of the SP, we extract an averaged profile line perpendicular to the etch trenches with several edges after the frontside etch, as shown in Fig.  for l-PCSi. In advance, leveling is performed, such that the upper plateaus of the SP are leveled out and set to 0. Even more, the leveling ensures that the maximum trench depth can be extracted accurately from the measurement data. A spatial step function zstep is designed to cover the specific shape of the trenches with rounded corners resulting from the dry-etching process: 6zstep=z0+Atanh⁡(scos⁡(2πfx+ϕ)). The parameter s in Eq. () has the default settings su=10 if cos⁡(2πfx+ϕ)>0 and sl=4 for the sharpness of the upper and lower edges, respectively. Additionally, f is the fixed spatial frequency of the trenches, z0 is the offset in height, and ϕ is the offset in the in-plane direction. Both the device layer thickness and the device height are determined as twice the amplitude A. The measurement is benchmarked with a stylus profilometer measurement, and very similar results are found. A similar approach is used for the extraction of the static deflection from the WLI scan of the cantilever. The plane correction is again done to minimize any impact from a tilted sample position, and the static deflection z(x) is fitted with Eq. (). A representative measurement and fitting procedure is shown in Fig. , again for l-PCSi.

Finally, we performed measurements of the wafer curvature with the l-PCSi, s-PCSi, and n-PCD thin films using an MX203-6-33 Wafer Geometry Gauge from E+H Metrology GmbH.

The material properties needed for the fitting procedures of the model by to the measured deflection curves of the cantilevers are summarized in Table . Standard values for SCSi are used from , while the Young's modulus of s-PCSi, l-PCSi, and PCSiC is calculated from the EB theory, the measured resonance frequency of the first EB mode, and the measured device layer thickness. We show the calculated stress distribution of the polycrystalline silicon device layer with small grains in the nanometer range (s-PCSi) for 40 devices with a length of 500 µm and a width of 50 µm in Fig. . The cantilever devices in each lower row are oriented parallel to the wafer flat, while the cantilever devices in each upper row are oriented perpendicular to the flat. Since the stress might not be isotropic, this approach allows us to distinguish between the stress values in two different directions (σ⟂ and σ∥) in close vicinity to minimize the impact of other parasitic effects, such as from microstructural variations. Results shown in the upper part of Fig.  represent the calculated mean stress σ0. We find compressive stress in most of the parallel devices and tensile stress in the perpendicular devices, with a huge difference in their mean values (σ‾0,∥ and σ‾0,⟂) of about 1542 MPa. However, the lower part of Fig.  shows the calculated gradient stresses in both directions and gives their mean values across the wafer in parallel and perpendicular directions, σ‾1,∥ and σ‾1,⟂, respectively. For the gradient stresses, we find negative, hence compressive, stress all over the wafer and a rather small difference in the mean values from parallel to perpendicular devices of about 24 MPa.

We performed the same study of 40 devices for each of five different thin films (SCSi, s-PCSi, l-PCSi, n-PCD, and PCSiC) with WLI and the model from and summarized the results in Fig. . The data of the m-PCD film, however, were too noisy for WLI characterization, due to the rough surface of the device layer. The data are plotted per device, while every fit of the beam's deflection accounts for the local thickness of the device layer extracted from the measurement of the step profile. Furthermore, the data are separated into parallel and perpendicular devices and into gradient and mean stress. When focusing on the mean stress σ0 representing the tilt of the beams, we find a low tensile mean stress of 67 MPa in SCSi. A tensile but very high σ0 of 1650 MPa is also measured for PCSiC for both directions. Moderate absolute values of mean stress up to absolute values of 500 MPa can be found for n-PCD but by changing the sign from negative (compressive) to positive (tensile) from parallel to perpendicular. Similar behavior is present in l-PCSi (σ0-absolute values up to 600 MPa). A much larger change can be found for s-PCSi (σ0-absolute values up to 1700 MPa), as shown in Fig. . We find a very consistent trend for all device layers for σ1, independent of the orientation of the test structure. Since the thickness of the device layer changes from the center to the edge of the wafer, symmetric changes of σ1 can be found for n-PCD and PCSiC, while the silicon device layers show rather constant values. In particular, the SCSi device layer does not show any curl of the beams, resulting in σ1=0.

A WLI measurement on a single device takes about 40 s, including the postprocessing steps. Repeated measurements are performed on the same device with ResonatorID = 182 on the l-PCSi wafer for 24 h. The gradient stress averaged for 210 measurements is calculated as σ1=40.95±1.47 MPa.

The direction-dependent mean stress σ0 measured for the polycrystalline silicon device layer with large grains in the range of ≈100 nm (l-PCSi), the polycrystalline silicon device layer with small grains in the nanometer range (s-PCSi), and the polycrystalline diamond device layer with small grains in the nanometer range (n-PCD) can be caused by several parameters during the deposition. Non-uniform temperatures in the CVD process, along with asymmetric gas flows, can lead to an anisotropic stress distribution in the wafer. Furthermore, the CTE is highly temperature-dependent, and even for SCSi and PCSi, the parameters differ by roughly a factor of 2 for different temperatures, as described by for SCSi and by for PCSi-SiO₂ stacks. The CTE is also dependent on the crystal orientation of the thin film, especially for SCSi, but also for PCSi, if there is a preferred growth direction. However, the identification of the microstructural origin of the direction-dependent stress is outside the scope of this work. Furthermore, the fitting procedure due to the leveling within the applied method is critical for the extraction of the correct mean stress, and the results shown for σ0 need to be used carefully, since small measurement and fitting uncertainties have a huge impact on σ0. A schematic is shown in Fig. , where the angle α represents the leveling error. The angle θ is the tilt of the beam at the anchor and is calculated as the sum of θ0 and θ1. Since θ1 is fixed by σ1 and the measured radius of the curvature R in Eq. (), the leveling error in a measurement is directly added to θ0 and hence to σ0. An uncertainty of the leveling resulting in a device tilt α=1 mrad for a 2 µm thick beam leads to a variation in σ0 of 90.7 and 341 MPa for SCSi and n-PCD, respectively.

The calculation of the local device layer stress is done with precise knowledge of the thickness at each position. The presented structures are used to characterize six thin films with WLI. Hence, 182 devices fabricated on half of a 4-inch (100 mm) wafer are fully automatically measured to extract the local thickness and static deflection information. With this information, it is possible to map the local properties, as shown for the thickness in Fig. . The maps show different distributions of the device layer depending on whether its thickness is locally either thinner or thicker. Wafer bonding, as done for the fabrication of the single-crystalline silicon device layer within an SOI process, leads to a pattern originating from the subsequent grinding process to define the thin film thickness. The other device layers fabricated from CVD are showing more random patterns related to the gas flow in the CVD reactor and the relative positions of the gas inlets. However, we find the standard deviation of the thickness to be minimal for the PCSi wafers used, medium for the SCSi and the m-PCD device layers, and maximal for the n-PCD thin film, respectively. Regions of the PCSiC device layer were destroyed during device fabrication; hence, no thickness map is shown for this thin film.

As already mentioned, the extraction of σ1 from the measured curvature of the cantilevers leads to a symmetric result for parallel and perpendicular devices. For the gradient stress, the influence of the device tilt is irrelevant, and a closer look at the effect of the local thin film thickness on σ1 is done in Fig. . To do so, we calculated the average thin film thickness h‾ for the 40 studied devices per device layer and show the difference between the gradient stress calculated with the local thin film thickness hloc and the one with h‾ per device in both directions, parallel and perpendicular to the wafer flat. While the difference is below 10 MPa in most of the measurements, it reaches up to 38 MPa for PCSiC at the edge of the wafer, indicating the high precision of the presented combination of film thickness and film stress measurement.

Stoney's equation, widely used to calculate the effective mean stress σ‾ of a film from wafer curvature measurement techniques, is very convenient since it needs the thin film thickness h as the only thin film input parameter: 7σ‾=ES1-νShS26hR. The radius R is measured optically or capacitively, and the properties of the substrate ES, νS, and hS (the Young's modulus, the Poisson ratio, and the thickness, respectively) are known. From considerations of the total force per unit width acting on the edge of the wafer f by , one finds an expression for the so-called stress thickness σ‾h 8f=σ‾h=∫-h/2h/2σuniaxialdz+fSurface+fInterface, where fSurface and fInterface are additional forces related to the surface of the thin film and the interface between substrate and thin film. Expressing the effective mean stress from Eq. () and inserting Eq. () leads to σ‾ depending only on the mean stress of the thin film, since the integral cancels out the stress gradient symmetric around the midplane of the thin film. Hence, it is clear that curvature measurements are only capable of measuring stress related to the mean stress in a thin film but cannot give any information on the gradient stress.

However, for the static deflection of MEMS devices, it is crucial to know both components to the residual stress. The list of three different MEMS cantilevers fabricated from l-PCSi, s-PCSi, and n-PCD in Fig.  compares the visible static deflection from the SEM image with the measured values of the effective mean stress from a capacitive wafer bow (WB) measurement and the mean values of σ‾0 and σ‾1 across 40 devices on each wafer, as described for Fig. . The l-PCSi cantilever shows an upwards static deflection, while the stress value from WB is negative. This discrepancy can be overcome by taking the positive σ¯1 into account. A situation like this is demonstrated in Fig. b, where the negative slope at the anchor and the superposition of the positive curl deflection lead to an overall positive deflection at the tip of the cantilever. Unfortunately, the measured σ‾0 value for this thin film does not fit the WB result due to possible limitations in the leveling procedure, also discussed above. Nevertheless, great accordance is found in the stress measurements for s-PCSi. For s-PCSi, the WB and the WLI values for σ‾0 are 115 and 113 MPa, while the averaged σ‾1 gives -164 MPa. These results describe a situation as shown in Fig. c. The static deflection of the s-PCSi cantilever shows a downwards bending with a rather high amplitude, as shown in the SEM image in Fig. . Finally, the n-PCD cantilever shows vanishing stress in the WB of 1 MPa, even though there is a slight static deflection visible in the SEM image of Fig. . The detailed analysis of the devices with WLI gives a rather high σ‾1=43 MPa, resulting from the small curvature and the high value of diamond's Young's modulus.

Further validation of the presented method is needed, since the gradient stress cannot be confirmed with wafer bow measurements. Possible alternatives to validate the results of this study are more elaborate techniques, like cross-sectional nanodiffraction XRD measurements or focused ion beam (FIB)-based methods. In the latter technique, a deformation analysis of a microstructure after sequential FIB-milling steps provides depth information on the stress in the studied film and hence the present stress gradient .

We present an MEMS test structure that is straightforward to fabricate with standard techniques of the MEMS industry in combination with an automated WLI measurement setup to determine local thin film thickness and film stress. The test structures are applied to six different device layers, revealing different thickness and static deflection distributions across the wafers. We calculate the local uniaxial mean stress σ0 and gradient stress σ1 following the FEM approach by . This calculation is done by dividing the deflection into a tilt and curl component and performing a fit of a quadratic function to the extracted deflection curve. By scanning devices across the wafer automatically, we get stress and thickness values at different positions on the wafer and with the orientation of the cantilever parallel and perpendicular to the wafer flat. We find local variation in the stress due to the device layer deposition processes and demonstrate that for polycrystalline silicon and diamond device layers, an orientation dependence of the stress is present. Furthermore, we want to highlight the impact of the gradient stress on the curl deflection of the devices, resulting in large deflection amplitudes often hidden by measurements of the average residual stress with curvature measurement techniques. These findings illustrate the need for a detailed knowledge of the thin film properties for the fabrication of MEMS devices, as stress in the device layer affects the fabricated MEMS device in several ways.

As demonstrated, WLI can provide information, static deflection, and thickness in a contactless, fast, and automated way; hence, this technique can be used in both academia and industry for stress inspection. The precision of the measured mean stress can be further improved by scans of larger regions supported by the silicon frame, leading to a more effective leveling of the device. Furthermore, the approach by , combining WLI scans of single-side clamped cantilevers and double-side clamped bridges, is promising. The study of bridges allows the extraction of a parameter related to the clamping properties to distinguish between simply supported and fixed clamped bridges. However, the measurement of bridges is not capable of measuring tensile stresses, since no static deflection is present. Hence, the combined study of bridges and cantilevers overcomes the problem of leveling, since supported areas of the device on both ends of the bridges can be used, and additional information on the clamping properties can lead to an even higher precision of the measurement.